Fault tolerance of L1 data cache memory induced by intrinsic parameters fluctuation in sub 10nm UTB-SOI MOSFETs

Currently, the development of models at higher level of abstractions (system-level) to be able to incorporate effects at lower levels of abstractions (process /transistor) is in demand. This thesis addresses issues to enabling computer system simulation model in the presence of cell failures in L1 d...

詳細記述

書誌詳細
第一著者: Ahmed, Rabah Abood
フォーマット: 学位論文
言語:英語
出版事項: 2013
主題:
オンライン・アクセス:http://psasir.upm.edu.my/id/eprint/56181/1/FK%202013%20116RR.pdf

類似資料