Fault tolerance of L1 data cache memory induced by intrinsic parameters fluctuation in sub 10nm UTB-SOI MOSFETs

Currently, the development of models at higher level of abstractions (system-level) to be able to incorporate effects at lower levels of abstractions (process /transistor) is in demand. This thesis addresses issues to enabling computer system simulation model in the presence of cell failures in L1 d...

पूर्ण विवरण

ग्रंथसूची विवरण

मुख्य लेखक:	Ahmed, Rabah Abood
स्वरूप:	थीसिस
भाषा:	अंग्रेज़ी
प्रकाशित:	2013
विषय:	Cache memory Metal oxide semiconductor field-effect transistors
ऑनलाइन पहुंच:	http://psasir.upm.edu.my/id/eprint/56181/1/FK%202013%20116RR.pdf