Design Methodology and Analysis of Hash Function based-on Field Programmable Gate Array for Hash-based Message Authentication Code Application

• Main Author: SHAMSIAH BINTI, SUHAILI
• Format: Thesis
• Language: English; English; English
• Published: Univeristi Malaysia Sarawak 2025
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://ir.unimas.my/id/eprint/49607/

Security has grown in importance as a study issue in recent years. Many cryptographic techniques have been created to raise the performance of different information-protection systems. One of the categories of cryptography is a hash function. In this research, the field-programmable gate array (FPGA) device from Altera is used because of its higher performance and smaller area implementation. For this purpose, cryptography hash functions are selected as a design target. These algorithms have been studied to improve the speed, area implementation, and power consumption. However, some trade-offs exist among higher performance, area implementation, and low-power design. Cryptographic algorithms are one of the most important aspects of the hardware implementation of embedded system design. They offer methods and systems for executing secure and authenticated transactions via the network. FPGAs are chosen because they can provide high-speed design, are simple to debug, are inexpensive, and have a rapid time to market. The main objective of this research is to formulate unfolding transformation factor 2 and factor 4 methods into hash function design. Additionally, low-power design techniques using state encoding in hash function design also need to be considered. All these design methodologies aim to confirm the effect of HDL coding style on the performance of hardware algorithms implemented on FPGA. This research focuses on unkeyed algorithm hash functions, such as MD5, SHA-1, RIPEMD-160, and SHA-256, to evaluate and compare the design's performance, area implementation, maximum clock frequency, and power consumption. In this research, an FPGA device named Arria II GX from Altera is used because of its higher performance and smaller area implementation compared with others. Pipelining and unfolding methods are applied to obtain high maximum frequency and high throughput of hash functions. The proposed SHA-1 designs, implemented on the Arria II GX EP2AGX45DF29C4, demonstrates an area of 548 combinational ALUTs and 907 registers. This is a significant reduction on the Stratix II GX. This indicates a 98.38% reduction in ALUTs and a 97.17% reduction in registers, highlighting the significant area efficiency of the proposed design. The most efficient design is the pipelined RIPEMD-160 on Arria II GX, which achieves a ratio of 3.5477 Mbps/ALUT, far greater than all other designs. In addition, the unfolding-based designs (factor 2 and factor 4) demonstrate competitive ratios of 0.5109 Mbps/ALUT and 0.5203 Mbps/ALUT, respectively, reflecting effective trade-offs between performance and resource utilisation. The proposed SHA-256 design with an unfolding factor of 4 had the greatest throughput of 4,196.30 Mbps, indicating a considerable improvement over earlier SHA-256 architecture. The proposed design demonstrates a 294.5% enhancement in throughput and the proposed architecture exhibits a 165.5% enhancement in throughput. A comparative analysis of HMAC-SHA-256 designs implemented on different FPGA platforms. With an area utilisation of 3,953 LUTs and 2,714 registers, the proposed HMAC-SHA256 design, when implemented on Altera Arria II GX with Quartus II 15.0, reaches a maximum frequency of 195.16 MHz.. The novelty and originality of this study lie in the combination of different methodologies that can improve the performance of hash function algorithms and integration of HMAC-SHA-256 designs. Besides, Gray encoding and clock gating can reduce the dynamic power dissipation caused by signal toggling. Furthermore, a combination of unfolding and pipelining can also increase the throughput of hash function algorithms.