Design method to transmit and receive source synchronous signals using source asynchronous

Field Programmable Gate Array (FPGA) yang berkos rendah menawarkan data dengan kelajuan terhad untuk saluran sumber segerak Low-Voltage Differential Signaling (LVDS) Input-Output (IO) tetapi kelajuan lebih tinggi untuk saluran sumber tidak segerak. Cyclone V adalah peranti berkos rendah yang menawar...

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Bibliographic Details
Main Author:	Ramachandran, Nathan
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK5105 Computer networks and Data transmission systems TK7868.D5 Digital electronics and Electronic circuit design
Online Access:	http://eprints.usm.my/33021/
Abstract	Abstract here

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