Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging

In this miniaturization era, previously, shrinking the technology node was used in order to maintain and improve the electrical performance of a device. However, this method is getting difficult due to the limitation of Silicon (Si) atomic size of the material in designing the integrated circuit (IC...

書誌詳細
第一著者:	Tan , Ai Heong
フォーマット:	学位論文
言語:	英語
出版事項:	2015
主題:	TK1-9971 Electrical engineering. Electronics. Nuclear engineering
オンライン･アクセス:	http://eprints.usm.my/40931/
Abstract	Abstract here

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