Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect

As the process technology advances, transistor size shrinks and more intellectual properties (IPs) are integrated onto chip. In order to accommodate the current complex functionalities as well as improving the performance of design, integrated circuit (IC) architecture has encouraged the integration...

書誌詳細
第一著者:	Chiew , Chong Giap
フォーマット:	学位論文
言語:	英語
出版事項:	2016
主題:	TK7800-8360 Electronics
オンライン･アクセス:	http://eprints.usm.my/41312/

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