Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors

The recent technology in the world of microprocessor is blended with complex chips that incorporate multiple processors dedicated for specific computational needs. Therefore, in any shared memory system, an arbitration technique plays an important role to allocate access to the shared resource...

पूर्ण विवरण

ग्रंथसूची विवरण
मुख्य लेखक: Akhtar, Mohammad Nishat
स्वरूप: थीसिस
भाषा:अंग्रेज़ी
प्रकाशित: 2013
विषय:
ऑनलाइन पहुंच:http://eprints.usm.my/45133/
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author Akhtar, Mohammad Nishat
author_facet Akhtar, Mohammad Nishat
author_sort Akhtar, Mohammad Nishat
description The recent technology in the world of microprocessor is blended with complex chips that incorporate multiple processors dedicated for specific computational needs. Therefore, in any shared memory system, an arbitration technique plays an important role to allocate access to the shared resources. The major challenge dealt in the proposed research is the achievement of maximum CPU utilization by exploiting its multiple cores with moderate bus bandwidth allocation and low system latency. In order to tackle the aforesaid problems, an intelligent adaptive arbitration technique has been proposed for the masters designed according to the traffic behaviour of the data flow. The proposed intelligent adaptive arbitration technique is implemented using STREAM, which is a synthetic benchmark program that measures computational rate and sustainable memory bandwidth. In terms of performance analysis, the proposed arbitration technique has been compared with the recent arbitration technique, such as adaptive arbitration technique, dynamic lottery bus arbitration, round robin arbitration and static fixed priority arbitration. To enhance the CPU utilization and bandwidth optimization, the proposed arbitration technique has been modelled using SystemC and OpenMP threads using the method of parallel programming to enable multi-core computing. Some recent arbitration technique achieves fair bus bandwidth allocation up to some extent but fails to achieve maximum CPU utilization, as the processor spends 95-96 % of their time idle and waits for cache misses to be satisfied. The proposed arbitration technique is a strong case in favour of maximum CPU usage and bandwidth optimization, as it consumes the processor cores up to 74% and also reduces the bandwidth fluctuation as well as latency.
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spelling usm-451332019-08-01T06:41:12Z http://eprints.usm.my/45133/ Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors Akhtar, Mohammad Nishat TK1-9971 Electrical engineering. Electronics. Nuclear engineering The recent technology in the world of microprocessor is blended with complex chips that incorporate multiple processors dedicated for specific computational needs. Therefore, in any shared memory system, an arbitration technique plays an important role to allocate access to the shared resources. The major challenge dealt in the proposed research is the achievement of maximum CPU utilization by exploiting its multiple cores with moderate bus bandwidth allocation and low system latency. In order to tackle the aforesaid problems, an intelligent adaptive arbitration technique has been proposed for the masters designed according to the traffic behaviour of the data flow. The proposed intelligent adaptive arbitration technique is implemented using STREAM, which is a synthetic benchmark program that measures computational rate and sustainable memory bandwidth. In terms of performance analysis, the proposed arbitration technique has been compared with the recent arbitration technique, such as adaptive arbitration technique, dynamic lottery bus arbitration, round robin arbitration and static fixed priority arbitration. To enhance the CPU utilization and bandwidth optimization, the proposed arbitration technique has been modelled using SystemC and OpenMP threads using the method of parallel programming to enable multi-core computing. Some recent arbitration technique achieves fair bus bandwidth allocation up to some extent but fails to achieve maximum CPU utilization, as the processor spends 95-96 % of their time idle and waits for cache misses to be satisfied. The proposed arbitration technique is a strong case in favour of maximum CPU usage and bandwidth optimization, as it consumes the processor cores up to 74% and also reduces the bandwidth fluctuation as well as latency. 2013-07 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/45133/1/Mohammad%20Nishat%20Akhtar24.pdf Akhtar, Mohammad Nishat (2013) Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors. Masters thesis, Universiti Sains Malaysia.
spellingShingle TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Akhtar, Mohammad Nishat
Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors
title Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors
title_full Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors
title_fullStr Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors
title_full_unstemmed Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors
title_short Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors
title_sort design and simulation of an intelligent adaptive arbiter for maximum cpu usage of multicore processors
topic TK1-9971 Electrical engineering. Electronics. Nuclear engineering
url http://eprints.usm.my/45133/
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