Study Of The Relationship Between Delta Delay And Adjacent Parallel Wire Length In 45 Nanometer Process Technology

Hierarchical design spans the complete framework of a design flow from Register Transfer Level (RTL), synthesis, place and route, timing closure and various other analyses before sign-off. Finer geometries and increasing interconnect density however have resulted signal integrity becoming the key is...

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Détails bibliographiques
Auteur principal:	Mohamed, Shamsul Anuar
Format:	Thèse
Langue:	anglais
Publié:	2014
Sujets:	TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Accès en ligne:	http://eprints.usm.my/46237/

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