Clock Gating Assertion Check An Approach Towards Efficient Verification Closure On Clock Gating Functionality
One of the power reduction techniques widely used in Register Transfer Level (RTL) stage of a design is clock gating. However, the addition of clock gating logics has increased the complexity of a design and therefore considerable amount of verification effort is required. The conventional verificat...
| 第一著者: | |
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| フォーマット: | 学位論文 |
| 言語: | 英語 |
| 出版事項: |
2017
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| 主題: | |
| オンライン･アクセス: | http://eprints.usm.my/46474/ |
| Abstract | Abstract here |