Clock Gating Assertion Check An Approach Towards Efficient Verification Closure On Clock Gating Functionality
One of the power reduction techniques widely used in Register Transfer Level (RTL) stage of a design is clock gating. However, the addition of clock gating logics has increased the complexity of a design and therefore considerable amount of verification effort is required. The conventional verificat...
| मुख्य लेखक: | |
|---|---|
| स्वरूप: | थीसिस |
| भाषा: | अंग्रेज़ी |
| प्रकाशित: |
2017
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| विषय: | |
| ऑनलाइन पहुंच: | http://eprints.usm.my/46474/ |