Clock Gating Assertion Check An Approach Towards Efficient Verification Closure On Clock Gating Functionality

One of the power reduction techniques widely used in Register Transfer Level (RTL) stage of a design is clock gating. However, the addition of clock gating logics has increased the complexity of a design and therefore considerable amount of verification effort is required. The conventional verificat...

書目詳細資料
主要作者:	Wang, Jian Zhong
格式:	Thesis
語言:	英语
出版:	2017
主題:	T Technology TK1-9971 Electrical engineering. Electronics. Nuclear engineering
在線閱讀:	http://eprints.usm.my/46474/

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