Numerical Analysis During Encapsulation Process Of Molded Underfill With Multi Flip Chip Package - Azmi, Muhammad Afiq (2018)
Nowadays, the technology of Integrated Circuit (IC) packaging has become a sophisticated design in addition to maintaining reliability and quality. Flip Chip Scale Package (CSP) is one of the IC chips which has a wafer-level packaged with spherical solder bump located on a grid with a pre-defined pitch between chip. In order to package it, Molded Underfill (MUF) was used which was an easier and faster process. However, the inconsistent flow of Epoxy Molding Compound (EMC) during encapsulation was more susceptible to unbalanced filling pattern, incomplete filling and internal void. Therefore, the EMC filling and flow through flip chip is very hard to visualize with actual experiment. In this study, the numerical approaches were used to study the encapsulation process of multi flip chip in the cavity. Thus, the numerical analysis is an appropriate approach to visualize during the encapsulation process. ANSYS FLUENT was used to simulate and analyze the fluid flow phenomena and consequences. The volume of fluid (VOF) technique was used for visualization of flow front. The flow visualization of MUF in the empty cavity and multi flip chip were presented. The flow behavior of EMC in different rheology models have been conducted. The Castro Macosko model has been identified as the best model to study flow behavior since it has considered the curing effect and degree of conversion. The numerical analysis is continued on stacking effect of flip chip. Triple stacked multi flip chip was found to have high retardation flow and large volume percentage during encapsulation. The relationship of rheological effect on stacking design of flip chip were studied accordingly. Changes in rheological effect and stacking design have influenced the EMC properties such as velocity, shear rate and viscosity.