Multilevel Three Phase Voltage Source Inverter With Simple Space Vector Pulse Width Modulation

• Main Author: Hossain, Md Liton
• Format: Thesis
• Language: English; English
• Published: 2016
• Subjects: T Technology (General); TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utem.edu.my/id/eprint/20614/; https://plh.utem.edu.my/cgi-bin/koha/opac-detail.pl?biblionumber=105976

Multilevel inverter has brought a great revolution in many industrial applications. The performances of multilevel inverter depend on the suitable modulation technique and topology. There a number of modulation techniques and topologies are already developed during last three decades. The most popular multilevel inverter topology is cascaded h-bridge inverter due to not having any clamping diode or capacitor and better performances. But it requires several number of separated DC sources that increase complexity as well as system cost. Three phase cascaded multilevel inverters with reduced number of DC voltage sources are proposed in this research that requires only 2, 3, 4, 5 and 6 separated DC sources for three phase 3, 4, 5, 6 and 7-level. Three phase cascaded multilevel inverters with single DC voltage source are also proposed in this research. On the other hand, the most popular modulation technique is space vector pulse width modulation (SVPWM) because of their easier digital realization, over modulation, high switching frequency, better DC bus utilization and lower THD. The complexity of switching control algorithms for multilevel inverter is increasing with the number of level due to increasing the number of switching states in space vector diagram. This research simplifies the space vector diagram that reduces the switching states to 26 from 27, 56 from 64, 98 from 125, 152 from 216 and 218 from 343 for 3, 4, 5, 6 and 7-level SVPWM respectively. The simplified strategy used in the research, the lower weighted digit values of switching states are omitted because performance of the multilevel inverter depends on the more weighted digit value of switching states. However it still has a constraint of having different number of switching states for different sub switching triangle of each sector. Therefore, the best four different active switching states will be selected for each switching triangle that makes the overall PWM algorithm simpler. The proposed three phase cascaded multilevel inverters (CMLI) based on simple space vector pulse width modulation have been modeled, simulated and evaluated using MATLAB/SIMULINK. Simulation results based on the proposed technique demonstrated the significant improvement in terms of output voltage and THD. The inverters of each level have been implemented using a single eZdsp control board embedded with TMS320F2812 processor. The results obtained from the experimental investigation for 3, 4, 5, 6 and 7 level inverter are consistent with the results obtained from the simulation. The three phase 7-level CMLI demonstrated 10.69% THD that is closest the IEE519 standard of 10% THD.