Characterization of reticle esd threshold voltage measurement for CMOS semiconductor manufacturing - Razman, Harriman (2022)
A reticle is a critical apparatus in patterning Integrated Circuit (IC) transfer to a silicon wafer during the lithography process and is considered the heart of a wafer fabrication process. It is very sensitive with accurate patterns designed into a nano-meter level on clear quartz. A typical Complementary Metal Oxide Semiconductor (CMOS) device requires 24 to 36 reticles equivalent to 24 to 36 mask layers for lithography process. An IC is considered completed after all reticle layers of a device are successfully transferred to the silicon wafer from the STI (Shallow Trench Isolation) designed to pad design or pad mask process. For a typical size of 40,000 wafer capacity a month, 7,000 to 8,000 reticles are actively exchanged within the lithography equipment to meet respective product and process requirements. An Advanced Semiconductor Material Lithography (ASML) lithography equipment can store three reticles at one time, and SilTerra has 18 lithography equipment. In a common semiconductor wafer fabrication business, reticles are owned by customers and supplied in limited units due to high cost. A reticle is extremely sensitive to electrostatic charge and may be damaged at a low Electrostatic Discharge (ESD) voltage level. The damage (ESD defect) is irreversible. SilTerra reported two cases of manufacturing interruption for 180 nm and 220 nm products equivalent to 60 days due to reticle damages despite being inline with the International Technology Roadmap for Semiconductors (ITRS) and Semiconductor Equipment Materials International (SEMI) standards. Consequently, 225 wafers were scrapped due to the reticle minor circuit patterning defects and 24 reticles were remade, costing about USD 232,000 for the company to compensate. The objective of this research was to characterize reticle ESD threshold voltage measurement at smaller technology nodes because the ESD threshold voltage defined by ITRS and SEMI standards is no longer applicable to resolve Binary reticle damage due to ESD at SilTerra. In this research, Binary and Phase-Shift Mask (PSM) reticles were discussed, analyzed, and justified to ensure sustainable solutions toward the cause of the problem. The method to resolve this issue was to perform a proper design of the experiment to find the threshold voltage. A 5 × 5 cell format consisting of 25 cells was designed in a 1 × 1 mm chipset on Binary and PSM reticles. Each cell consisted of single and dense line features of 80 nm, 90 nm, 110 nm, 130 nm, and 160 nm technology nodes used by SilTerra in their product diversity. An electrostatic field induction and direct discharge tests were conducted on each reticle to obtain the breakdown voltage. KLA-Tencor STARlight and microscope inspections were performed before and after each test for inspecting ESD defects. The Breakdown Voltage (BV) for a Binary reticle was correlated with a spur to border or metal to metal gap width at the linear relationship of R2 = 97.3% and derived as