VHDL implementation of pipelined DLX microprocessor

The 32-bit load/store DLX processor architecture is a generic RISC processor designed by Hennessy and Patterson for pedagogical purposes. The DLX processor design abstracts many features of general-purpose commercial processors, and is a well-understood computer architecture, providing a good archit...

書誌詳細
第一著者:	Anthony, Ignatius Edmond
フォーマット:	学位論文
言語:	英語
出版事項:	2008
主題:	QA75 Electronic computers. Computer science TK Electrical engineering. Electronics Nuclear engineering
オンライン･アクセス:	http://eprints.utm.my/11462/1/IgnatiusEdmondAnthonyFKE2008.pdf

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