A computer aided design software module for clock tree synthesis in very large scale integration design
With the evolution of Very Large Scale Integration (VLSI) fabrication technology, circuit size has grown and line width has decreased. In effect, the transistor transit time and the time to drive signal lines across chips have also decreased. Thus, interconnections have become the dominating fact...
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| 格式: | Thesis |
| 語言: | 英语 |
| 出版: |
2008
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| 在線閱讀: | http://eprints.utm.my/17986/1/ChewEikWeeMFKE2008.pdf |