Style de citation APA (7e éd.)

Hew, K. Y. (2008). Verilog design of bist on AES256 processor core with FPGA implementation.

Style de citation Chicago (17e éd.)

Hew, Kean Yung. Verilog Design of Bist on AES256 Processor Core with FPGA Implementation. 2008.

Style de citation MLA (9e éd.)

Hew, Kean Yung. Verilog Design of Bist on AES256 Processor Core with FPGA Implementation. 2008.