Hew, K. Y. (2008). Verilog design of bist on AES256 processor core with FPGA implementation.
शिकागो शैली (17वां संस्करण) प्रशस्ति पत्रHew, Kean Yung. Verilog Design of Bist on AES256 Processor Core with FPGA Implementation. 2008.
एमएलए (9वां संस्करण) प्रशस्ति पत्रHew, Kean Yung. Verilog Design of Bist on AES256 Processor Core with FPGA Implementation. 2008.
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