Functional test generation using micro operation fault model
As semiconductor technology advances further into nanometer regime, integrated circuit testing and validation continues to play a very important role to ensure high quality product. Conventionally, test patterns are generated from a gate level netlist using test generation tool. However, as the digi...
| Auteur principal: | |
|---|---|
| Format: | Thèse |
| Langue: | anglais |
| Publié: |
2011
|
| Sujets: | |
| Accès en ligne: | http://eprints.utm.my/33347/1/OngHuiYienMFKE2011.pdf |