Functional test generation using micro operation fault model
As semiconductor technology advances further into nanometer regime, integrated circuit testing and validation continues to play a very important role to ensure high quality product. Conventionally, test patterns are generated from a gate level netlist using test generation tool. However, as the digi...
| 第一著者: | |
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| フォーマット: | 学位論文 |
| 言語: | 英語 |
| 出版事項: |
2011
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| 主題: | |
| オンライン･アクセス: | http://eprints.utm.my/33347/1/OngHuiYienMFKE2011.pdf |