Hardware acceleration of 2D convolution using systolic array

• Auteur principal: Wong, Xue Yuan
• Format: Thèse
• Langue: anglais
• Publié: 2015
• Sujets: TK Electrical engineering. Electronics Nuclear engineering
• Accès en ligne: http://eprints.utm.my/53576/1/WongXueYuanmfke2015.pdf

Two-dimensional convolution is a prevalent mathematical operation used in different areas of digital signal processing such as image processing, video processing and analog signal transmission. The computation intensive nature of 2D convolution operation along with the stringent demand of real-time image processing in term of response time and throughput rate dismiss the viability of general-purpose processor to be used as part of the image processing solutions. Thus, the design work of a fully-dedicated 2D convolution hardware based on systolic array architecture with integrated pipeline design is proposed in this project in order to achieve optimum hardware performance in term of processing time and throughput rate. To achieve the objective, the entire hardware design is fully described in SystemVerilog and cut-set systolization procedure is applied to map 2D convolution algorithm to a 3 x 3 based systolic array hardware design. Upon the end of design and integration, the accelerated 2D convolution hardware design goes through performance benchmark. Based on the performance benchmark report, the implemented 2D convolution hardware is capable to achieve a throughput rate of 168M outputs per second. In addition, it takes 1.54 ms to complete the execution of 2D convolution based on 512 x 512 grayscale image. In comparison with general-purpose processor, the implemented design outperforms general-purpose processor in term of execution speed by 43%. The performance breakthrough marks an important milestone to the pipelined 2D convolution hardware design based on systolic array architecture as the design is proven to be essential for the future use of real-time image processing.