Block-based neural network mapping on graphics processor unit
Block-based neural network (BbNN) was introduced to improve the training speed of artificial neural network. Various works had been carried out by previous researchers to improve training speed of BbNN system. Multithread BbNN training on field-programmable gate array (FPGA) limits training speed du...
| मुख्य लेखक: | Ong, Chin Tong |
|---|---|
| स्वरूप: | थीसिस |
| भाषा: | अंग्रेज़ी |
| प्रकाशित: |
2015
|
| विषय: | |
| ऑनलाइन पहुंच: | http://eprints.utm.my/53959/1/OngChinTongMFKE2015.pdf |
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समान संसाधन
-
VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm
द्वारा: Rajah, Avinash
प्रकाशित: (2005) -
An evolvable block-based neural network architecture for embedded hardware
द्वारा: Paramasivam, Vishnu
प्रकाशित: (2013) -
RTL design of modular arithmetic processor (MAP) core for prime finite field arithmetic, GF(P)
द्वारा: Liew, Meng Wei
प्रकाशित: (2008) -
ARM processor emulator
द्वारा: Mohd. Hashim, Mohamad Hasruzairin
प्रकाशित: (2015) -
VHDL modelling and asic design of a shortest-path processor core for network routing
द्वारा: Teoh, Giap Seng
प्रकाशित: (2003)