Verilog design of input/output processor with built-in-self-test

This project has a final goal of designing an I/O processor (IOP) with embedded built-in-self-test (BIST) capability. The IOP core design was originally design in VHDL modeling has been migrated to Verilog HDL modeling in this project. BIST is one of the most popular test technique used nowadays. Th...

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Bibliographic Details
Main Author:	Goh, Keng Hoo
Format:	Thesis
Language:	English
Published:	2007
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/5959/1/GohKengHooMFKE2007.pdf

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