Verilog design of input/output processor with built-in-self-test

This project has a final goal of designing an I/O processor (IOP) with embedded built-in-self-test (BIST) capability. The IOP core design was originally design in VHDL modeling has been migrated to Verilog HDL modeling in this project. BIST is one of the most popular test technique used nowadays. Th...

وصف كامل

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	Goh, Keng Hoo
التنسيق:	أطروحة
اللغة:	الإنجليزية
منشور في:	2007
الموضوعات:	TK Electrical engineering. Electronics Nuclear engineering
الوصول للمادة أونلاين:	http://eprints.utm.my/5959/1/GohKengHooMFKE2007.pdf

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