Ch'ng, H. S. (2007). Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing.
Style de citation Chicago (17e éd.)Ch'ng, Heng Sun. Graph Processing Hardware Accelerator for Shortest Path Algorithms in Nanometer Very Large-scale Integration Interconnect Routing. 2007.
Style de citation MLA (9e éd.)Ch'ng, Heng Sun. Graph Processing Hardware Accelerator for Shortest Path Algorithms in Nanometer Very Large-scale Integration Interconnect Routing. 2007.
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