Hardware based accelerator for database query using M-tree

Fast indexing is an indexing methods that sort the database and enable content to be accessed quickly. Fast query is part of fast indexing which able to perform the query within a narrow range to reduce the query time. In fast query, machine learning has played an important role on automate the task...

Description complète

Détails bibliographiques
Auteur principal:	Chai, Kah Hieng
Format:	Thèse
Langue:	anglais
Publié:	2018
Sujets:	TK Electrical engineering. Electronics Nuclear engineering
Accès en ligne:	http://eprints.utm.my/79262/1/ChaiKahHiengMFKE2018.pdf

Documents similaires

Principal component analysis hardware acceleration
par: Ng, Yee Wei
Publié: (2020)

Hardware acceleration of secure hash algorithm 3
par: Ng, Lai Boon
Publié: (2020)

Hardware accelerator implementation of colour correction algorithm
par: Loh, Shu Ting
Publié: (2020)

Face detection hardware accelerator using C-based high-level synthesis
par: Yeap, Han Chien
Publié: (2018)

Hardware acceleration of 2D convolution using systolic array
par: Wong, Xue Yuan
Publié: (2015)

Electrocardiogram QRS detection hardware accelerator for ASIC implementation
par: Lim, Zhi Qing
Publié: (2020)

Support vector machine hardware accelerator for tongue colour diagnosis
par: Thiah, Amanda Su Lin
Publié: (2020)

8192 bit Rivest-Shamir-Adleman data encryption hardware accelerator
par: Chew, Yen Wen
Publié: (2015)

Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
par: Mohammed, Mohammed Isam Eldin Hassan
Publié: (2020)

Hardware-based biometric encryption implementation with Gauss-Jordan algorithm accelerator core in field programmable gate arrays
par: Liew, Tek Yee
Publié: (2011)

An embedded system for networking security applying cryptographic acceleration in field programmable gate array hardware
par: Paramasivam, Vishnu
Publié: (2009)

Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing
par: Ch'ng, Heng Sun
Publié: (2007)

Hardware implementation using FPGA for barcode reader
par: Marzuki, Ade Syaheda Wani
Publié: (2008)

Implementation of instruction decoding logic using hardware and software
par: Su, Chee Siong
Publié: (2010)

Hardware-based genetic algorithm implementation in field programmable gate arrays
par: Balakrishnan, Sathivellu
Publié: (2012)

Implementation of reconfigurable viterbi decoders in hardware
par: Noor Batcha, Mohamed Farid
Publié: (2010)

Hardware core of pipelined thinning algorithm
par: Noordin, Mohamad Amin
Publié: (2015)

Magnetohydrodynamic accelerator with equilibrium plasma
par: Sukarsan, Sukarsan
Publié: (2009)

Magnetohydrodynamic accelerator with equilibrium plasma
par: Sukarsan, Sukarsan
Publié: (2010)

A hardware architecture of prewitt edge detection
par: Seif, Aramesh
Publié: (2009)

Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination
par: Oh, Eng Wei
Publié: (2015)

Design and implementation of OFDM transmitter and receiver on FPGA hardware
par: Kadiran, Kamaru Adzha
Publié: (2005)

Hardware implementation of naive bayes classifier for malware detection
par: Al Hussein, Yahya Khaled
Publié: (2021)

Power efficient blockchain miner accelerator design
par: Lim, Calvin
Publié: (2022)

Accelerated Verilog Simulator Using Application Specific Microprocessor
par: Tan Tze Sin, Tze Sin
Publié: (2017)

Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing
par: Teo, Hong Yap
Publié: (2015)

High resolution impulse analysing system - hardware and software implementation
par: Kassim, Ahmad Tarmimi
Publié: (2015)

Modeling of image processing algorithms for hardware-software co-simulation
par: Isa, Ibrahim
Publié: (2015)

Trees inventory system based on RFID at Frim
par: Ainul Hazmin A.Hamid
Publié: (2009)

Numerical simulation magnetohydrodynamic accelerator with nonequilibrium air plasma
par: Qazi , Hummad Habib
Publié: (2010)

Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust
par: Zainurin, Siti Nadhirah
Publié: (2021)

Register transfer level design of compression processor core using verilog hardware description language
par: Mohd. Sabri, Roslee
Publié: (2007)

Hardware-accelerated localization for automated license plate recognition system
par: Chin, Teck Loong
Publié: (2014)

A hardware architecture of stateless open digest spam fingerprinting unit
par: Monemi, Alireza
Publié: (2010)

Convolution and max pooling layer accelerator for convolutional neural network
par: Goh, Jinn Chyn
Publié: (2020)

Hardware implementation of coordinate rotation digital computer in field programmable gate array
par: Mohd. Sazali, Mohd. Ilyas Sobirin
Publié: (2012)

An embedded cryptosystem implementing symmetric cipher and public-key crypto algorithms in hardware
par: Hau, Yuan Wen
Publié: (2005)

Hash function of cryptographically secure pseudorandom number generator for hardware root-of-trust
par: Ong, Elaine Ei Ling
Publié: (2021)

Register-transfer-level Hardware Trojan classification boosted with gate-level features
par: Choo, Hau Sim
Publié: (2022)

Comparative study on dielectric performance between vegetable-based and mineral-based oil under accelerated thermal ageing and loaded distribution transformer
par: Mohd.Taib, Mohd. Fikri Hilmi
Publié: (2018)