Implementation of image compression algorithm using field programmable gate array (FPGA)
Also available in printed version
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| Format: | Master's thesis |
| Language: | English |
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Universiti Teknologi Malaysia
2025
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| Online Access: | https://utmik.utm.my/handle/123456789/42827 |
| Abstract | Abstract here |
| _version_ | 1854975127846912000 |
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| author | Zulfakar Aspar |
| author2 | Khalil Mohd. Hani, supervisor |
| author_facet | Khalil Mohd. Hani, supervisor Zulfakar Aspar |
| author_sort | Zulfakar Aspar |
| description | Also available in printed version |
| format | Master's thesis |
| id | utm-123456789-42827 |
| institution | Universiti Teknologi Malaysia |
| language | English |
| publishDate | 2025 |
| publisher | Universiti Teknologi Malaysia |
| record_format | dspace |
| record_pdf | Abstract |
| spelling | utm-123456789-428272025-03-11T18:26:33Z Implementation of image compression algorithm using field programmable gate array (FPGA) Zulfakar Aspar Khalil Mohd. Hani, supervisor Field programmable gate arrays Image compression Image processing Also available in printed version Huffman coding is one of the important components in image and video compression system. Huffman Coding is a lossless compression method, which exploits statistical redundancy of the data to be encoded. The algorithm also is uniquely decodable and can be instantaneously decoded. Due to its efficiency, Huffman algorithm is used in many image compression standards such as JPEG, MPEG, MPEG II and H.261. Even though there are a lot of available hardware with compression algorithm, there is no report indicated that there is any Malaysian made. Besides, this is among the first attempt to implement any compression algorithm in a hardware! This paper presents an FPGA based Huffman Coder that can perform real time compression. As an application example, a JPEG Decoder was built which consists of JPEG Huffman Decoder, Inverse Scalar Quantizer and Inverse Discrete Cosine Transform. The design was implement in a Field Programmable Gate Array (FPGA). FPGA implementation provides the benefits of reconfigurability, speed of operations and shorter development cycle (compared to VLSI implementation). zulraizam UTM 143 p. Thesis (Master of Engineering (Electrical)) - Universiti Teknologi Malaysia, 1999 2025-03-11T05:20:44Z 2025-03-11T05:20:44Z 1999 Master's thesis https://utmik.utm.my/handle/123456789/42827 vital:148824 valet-20220925-130340 ENG Closed Access UTM Complete Unpublished Completion application/pdf Universiti Teknologi Malaysia |
| spellingShingle | Field programmable gate arrays Image compression Image processing Zulfakar Aspar Implementation of image compression algorithm using field programmable gate array (FPGA) |
| thesis_level | Master |
| title | Implementation of image compression algorithm using field programmable gate array (FPGA) |
| title_full | Implementation of image compression algorithm using field programmable gate array (FPGA) |
| title_fullStr | Implementation of image compression algorithm using field programmable gate array (FPGA) |
| title_full_unstemmed | Implementation of image compression algorithm using field programmable gate array (FPGA) |
| title_short | Implementation of image compression algorithm using field programmable gate array (FPGA) |
| title_sort | implementation of image compression algorithm using field programmable gate array fpga |
| topic | Field programmable gate arrays Image compression Image processing |
| url | https://utmik.utm.my/handle/123456789/42827 |
| work_keys_str_mv | AT zulfakaraspar implementationofimagecompressionalgorithmusingfieldprogrammablegatearrayfpga |