A built-in self-testable bit-slice processor / Ibrahim Abubakr M.

類似資料

• Verilog design of input/output processor with built-in-self-test
  著者:: Goh, Keng Hoo
  出版事項: (2007)
• Multi-core 16-bit CPUs for PLC processor
  著者:: Gan, Chi Qian
  出版事項: (2022)
• Software-based self-test with scan design at register transfer level for 16-bit RISC processor
  著者:: Ang, Kim Chuan
  出版事項: (2010)
• Design for testability method at register transfer level
  著者:: Paraman, Norlina
  出版事項: (2016)
• VHDL design of A 32-Bit RISC processor core for FPGA implementation
  著者:: Marsono, Muhammad Nadzir
  出版事項: (2001)