Analysis and study of powerefficient sar adc for active rfid sensor

• Auteur principal: Ahmad Azzreen, Dalawi
• Format: Thèse
• Langue: anglais
• Publié: 2021
• Sujets: T Technology (General); TA Engineering (General). Civil engineering (General)
• Accès en ligne: http://umpir.ump.edu.my/id/eprint/34770/1/15.Analysis%20and%20study%20of%20powerefficient%20sar%20adc%20for%20active%20rfid%20sensor.pdf

This thesis introduced an energy-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) specialized to the active sensors for low-power radio frequency identification (RFID) tag system. As part of the Internet of Things (IoT) transformation, RFID is widely used. In the application where the power supply is limited, power consumption is always a notable criterion as analog circuits such as the ADC circuit, regulator circuit, rectifier circuit and radio frequency (RF) are the common power demanding parts in the system. Normally, the requirement for a longer battery performance is closely related to low-power consumption. For the application active RFID sensor in which requires low to moderate resolution and speed as well as low-power consumption, SAR is usually used as its part of the ADC circuit. Therefore, the power-efficient SAR ADC is presented in this work. The block of SAR ADCs such as the comparator block, digital-to-analog converter (DAC) block, and sampler block is designed to meet the requirement of a low-power consumption performance measurement. This thesis at first will explores the differences between multiple ADC techniques in the previous works. The proposed SAR ADC is presented to enhance the power consumption of SAR ADC in the active RFID sensor application through the implementation of a single-input comparator with the switched-capacitor DAC. In this form of architecture, there is only one input to the comparator, and only one set and a split sampling capacitor in the switched capacitor DAC to generate the required reference levels. The difference in input and output voltage of the proposed SAR ADC is the indication for the low-power design. The influence of parasitic capacitance is reduced to the extent of becoming a non-factor. The parameters of the SAR ADC are the resolution of 8-bit, the sampling frequency of 500 kHz, the supply voltage of 1 V, and the 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. The power consumption of the proposed SAR ADC is 2.3 μW which is estimated at around 25.8% improvement from the previous work. The demands for low-power consumption of RFID active sensor is well examined. The validity of the proposed design has been proven by the simulation results.