Formulation and Mitigation of Soft Error in CMOS Memory System by using Transmission Gate
The downscaling of technology has resulted in increased packing density in CMOS technology and thus, a worrying uptick in single event upset susceptibility in contemporary technology. SRAMs in particular, which now occupy up to 70% of all chip size, are vulnerable to errors from single event u...
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| Format: | Thesis |
| Language: | English English English |
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Universiti Malaysia Sarawak
2025
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| Online Access: | http://ir.unimas.my/id/eprint/48979/ |
| Abstract | Abstract here |