Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work
Debug and diagnosis in post-silicon challenges the technological advancement in Physical-to-Layout Mapping capabilities. Areas that require such innovation are fault isolation work in failure analysis of semiconductor devices, at post-silicon stage. Since fault isolation work begins at Register Tran...
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| 格式: | Thesis |
| 語言: | 英语 |
| 出版: |
2017
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| 在線閱讀: | http://eprints.usm.my/39594/ |
| Abstract | Abstract here |