Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
As the process technology advances, transistor size shrinks and more intellectual properties (IPs) are integrated onto chip. In order to accommodate the current complex functionalities as well as improving the performance of design, integrated circuit (IC) architecture has encouraged the integration...
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| フォーマット: | 学位論文 |
| 言語: | 英語 |
| 出版事項: |
2016
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| 主題: | |
| オンライン･アクセス: | http://eprints.usm.my/41312/ |