| 要約: | Logic simulation is an important step in Very Large Scale Integration (VLSI)
IC development. Advancement in Hardware Description Language (HDL) has made
Verilog a widely adopted language used to model digital circuit and verification test
bench. Electronic Design Automation (EDA) vendor provides software and hardwareassisted
approaches to carry out simulations. However, software-based simulator is
slow whereas hardware-assisted simulator does not offer the same simulation fidelity
stipulated in Verilog. In this research project, a hardware-assisted Verilog simulator,
VerCPU System, was proposed to address shortcomings in existing platforms. The
simulator core is a custom designed application specific microprocessor specifically
adapted to handle Verilog simulation. The microprocessor computes Verilog data in
its native form while supporting event-driven parallelism directly to achieve speed
supremacy. Being a compiled-code simulator, simulation fidelity compliancy is
retained to offer the same result and visibility like the software-based solution. A
functional system, VerCPU, was developed and prototyped on a Field Programmable
Gate Array (FPGA) development board. This system was successfully verified and
benchmarked against a software-based compiled-code simulator, i.e. Synopsys VCS®.
VerCPU System can already achieve up to 6 times speed superiority with basic speed
improvement techniques applied. The simulator had proven to be a viable alternate
Verilog simulator to meet future simulation needs.
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