Accelerated Verilog Simulator Using Application Specific Microprocessor
Logic simulation is an important step in Very Large Scale Integration (VLSI) IC development. Advancement in Hardware Description Language (HDL) has made Verilog a widely adopted language used to model digital circuit and verification test bench. Electronic Design Automation (EDA) vendor provides...
| Auteur principal: | Tan Tze Sin, Tze Sin |
|---|---|
| Format: | Thèse |
| Langue: | anglais |
| Publié: |
2017
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| Sujets: | |
| Accès en ligne: | http://eprints.usm.my/45788/ |
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