Study Of The Relationship Between Delta Delay And Adjacent Parallel Wire Length In 45 Nanometer Process Technology
Hierarchical design spans the complete framework of a design flow from Register Transfer Level (RTL), synthesis, place and route, timing closure and various other analyses before sign-off. Finer geometries and increasing interconnect density however have resulted signal integrity becoming the key is...
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| フォーマット: | 学位論文 |
| 言語: | 英語 |
| 出版事項: |
2014
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| 主題: | |
| オンライン･アクセス: | http://eprints.usm.my/46237/ |