VLSI Implementation Of A Systolic Array Viterbi Decoder
This project is on developing a Vi terbi decoder which uses the trace-back method structured in a systolic array fashion. It is believed that this architecture can reduce the size of the decoder as it minimizes the connections between component modules and requires a smaller storage space. The trace...
| Auteur principal: | |
|---|---|
| Format: | Thèse |
| Langue: | anglais |
| Publié: |
1995
|
| Sujets: | |
| Accès en ligne: | http://eprints.usm.my/63228/ |
| Abstract | Abstract here |