VLSI Implementation Of A Systolic Array Viterbi Decoder
This project is on developing a Vi terbi decoder which uses the trace-back method structured in a systolic array fashion. It is believed that this architecture can reduce the size of the decoder as it minimizes the connections between component modules and requires a smaller storage space. The trace...
| मुख्य लेखक: | |
|---|---|
| स्वरूप: | थीसिस |
| भाषा: | अंग्रेज़ी |
| प्रकाशित: |
1995
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| विषय: | |
| ऑनलाइन पहुंच: | http://eprints.usm.my/63228/ |
| Abstract | Abstract here |