VLSI Implementation Of A Systolic Array Viterbi Decoder

This project is on developing a Vi terbi decoder which uses the trace-back method structured in a systolic array fashion. It is believed that this architecture can reduce the size of the decoder as it minimizes the connections between component modules and requires a smaller storage space. The trace...

詳細記述

書誌詳細
第一著者: Mohd. Noh, Norlaili
フォーマット: 学位論文
言語:英語
出版事項: 1995
主題:
オンライン・アクセス:http://eprints.usm.my/63228/
Abstract Abstract here

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