Skip to content
MyTheses
  • Feedback
  • Book Bag: 0 items (Full)
  • HOME
  • MYTHESES
  • BLOG
  • AI ASSISTANT
  • INSTITUTION
  • GUIDE & TUTORIAL
  • CONTACT
    • English
    • Français
    • 日本語
    • 中文(简体)
    • 中文(繁體)
    • اللغة العربية
    • हिंदी
Advanced
  • Implementation of image compre...
  • Cite this
  • Text this
  • Print
  • Export Record
    • Export to RefWorks
    • Export to EndNoteWeb
    • Export to EndNote
  • Add to Book Bag Remove from Book Bag
  • Permanent link

QR Code

Implementation of image compression algorithm using field programmable gate array (FPGA)

Bibliographic Details
Main Author: Aspar, Zulfakar
Format: Thesis
Published: 1999
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
  • Holdings
  • Description
  • Similar Items
  • Staff View

Similar Items

  • Design and implementation of 16 bit DSP core processor using field programmable gate array (FPGA)
    by: Abdul Rahman, Abdul Aziz
    Published: (2003)
  • Hardware-based genetic algorithm implementation in field programmable gate arrays
    by: Balakrishnan, Sathivellu
    Published: (2012)
  • Implementation of direct torque control of induction machines utilizing Digital Signal Processor (DSP) and Field Programmable Gate Arrays (FPGA)
    by: Toh, Chuen Ling
    Published: (2005)
  • Hardware implementation of coordinate rotation digital computer in field programmable gate array
    by: Mohd. Sazali, Mohd. Ilyas Sobirin
    Published: (2012)
  • Hardware-based biometric encryption implementation with Gauss-Jordan algorithm accelerator core in field programmable gate arrays
    by: Liew, Tek Yee
    Published: (2011)

Search Options

  • Search History
  • Advanced Search

Find More

  • Browse the Catalog
  • Browse Alphabetically
  • Explore Channels
  • Course Reserves
  • New Items

Need Help?

  • Search Tips
  • Ask a Librarian
  • FAQs