The effect of stainless steel substrate temperature of silicon interlayer coating using PVD method

Also available in printed version

Bibliographic Details
Main Author:	Syed Mohd. Ridzuan Syed Pauzi
Other Authors:	Muhamad Azizi Mat Yajid, supervisor
Format:	Bachelor thesis
Published:	Universiti Teknologi Malaysia 2025
Subjects:	Mechanical engineering
Online Access:	https://utmik.utm.my/handle/123456789/103478
Abstract	Abstract here

Internet